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MAX7060
280MHz to 450MHz Programmable
ASK/FSK Transmitter
Table 9. IO Configuration 1 (IOConf1) Register (Address: 0x05)
BIT
NAME
GPO2 output selection
FUNCTION
CS _DEV
0
1
1
Bit 2
X
0
0
Bit 1
X
0
0
Bit 0
X
0
1
GPO2_MOD
SPI Data Output
lockdet
—
6:4
gp2s[2:0]
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
ckout
—
—
nock
—
—
GPO1 output selection
Bit 2
0
0
Bit 1
0
0
Bit 0
0
1
GPO1
lockdet
—
2:0
gp1s[2:0]
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
ckout
—
—
nock
—
—
where:
—
nock
ckout
Reserved signals
No-clock flag (1) if crystal oscillator is disabled, and (0) if clock activity is observed
Clock output signal, according to programmed dividers (ckdiv[2:0])
lockdet PLL lock-detect flag
Table 10. ASK Digital Shaping Time Step (Tstep) Register (Address: 0x06)
BIT
3:0
NAME
tstep[3:0]
FUNCTION
Time interval value used in digital shaping, in increments of 4/f XTAL
Table 11. PA Digital Shaping Amplitude Step (PAstep) Register (Address: 0x07)
BIT
4:0
NAME
pastp[4:0]
FUNCTION
Power step in digital shaping, in increments of 1dB
Table 12. PA Power (PApwr) Register (Address: 0x08)
BIT
4:0
NAME
papwr[4:0]
Final PA output power setting
FUNCTION
Table 13. FSK High-Frequency 0 (FHigh0) Register (Address: 0x09)
BIT
7:0
NAME
fhi[15:8]
FUNCTION
8-bit upper byte of high-frequency divider for FSK
Maxim Integrated
23
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